A multicore system which executes processing by using a plurality of CPUs (Central Processing Units) adopts a structure in which the CPUs each have a cache memory and all the CPUs share a large-capacity, low-speed external memory (main memory or the like). It is also known that, in each of the CPUs, a write buffer is provided between the cache memory and the external memory in order to absorb the time for writing data from the cache memory to the external memory.
In the multicore system, data sharing among the CPUs is indispensable. Therefore, the cache memories each have a function called a snoop to keep coherency of cache data (cache coherency) among the CPUs. When the snoop is generated, the CPU receiving the snoop waits an access request from a CPU core to the cache memory, which leads to performance deterioration.
There has been proposed an art to store addresses included in access requests passing through a common bus, in a table of a cache system of each of CPUs, and when an address of a received access request is stored in the table, inhibit an access to the cache memory in response to this access request (for example, refer to Patent Document 1). There has also been proposed an art in which, regarding each area in an external memory, information indicating whether or not data is cached in each of the CPUs is stored in a table included in each of the CPUs, and a destination of a snoop request is limited based on the information stored in the tables to reduce a traffic (for example, refer to Patent Document 2).
[Patent Document 1] Japanese Laid-open Patent Publication No. 09-293060
[Patent Document 2] Japanese Laid-open Patent Publication No. 09-311820
In a cache memory having a snoop function, an access from a CPU core to the cache memory and an access to the cache memory by the snoop are performed exclusively. Therefore, when many snoops are generated, the access from the CPU core to the cache memory is often kept waited, which leads to performance deterioration.